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Estimating Stuck at Coverage percentage through scan flops during scan
Bhuyan S., Jain M.,
Published in Institute of Electrical and Electronics Engineers Inc.
In SoC, every module must function properly even after fabrication. If a module is behaving properly in terms of it's functionality during the designing of the chip, it must be ensured that the module should work properly after the chip is being fabricated. This is because due to some manufacturing defect, the module may not function properly. As the process of manufacturing requires fine precision, the chip must undergo testing during it's designing phase. This is called design for testing. In SoC, it's an utmost important to insert DFT ( Design For Testing ) components to all the IP and the modules present in the SoC. There are many modules in SoC which contains thousands of flops. It's scan version is scan flops. During design for testing, a sequence of data is being sent to the scan flops which are stitched to each other in serial manner. The data is captured, shifted from the previous flop to the next flop and the value is loaded. The final output sequence is obtained from the final flip flop and is observed for proper functionality. Propagating signal from one flop to another flop is not an easy task as the sequence needs to be propagated from flops to flops thus experiencing delay, glitch, etc. All the scan flops must receive signals from proper source to avoid coverage loss. Thus early testability of RTL is necessary which detects the fault if the flop is not receiving proper signal and if some signal dedicated for scan operation is not properly constrained. Generally, the scan coverage may vary from 20 % to 100 %. There are partition achieving 100 % coverage but there are some partition too having coverage of just 20 % and the aim is to increase the scan coverage thus minimising the coverage loss to ensure proper scan operation. © 2019 IEEE.