VLSI design techniques are the key to reengineering the digital gadgets of any kind which are needed to be operated with lower power to ensure a longer backup time. Power reduction in Arithmetic Logic Unit (ALU) is needed for this requirement. Multipliers and adders are the most important structures which use a larger fraction of power in such arithmetic units. This paper analyses the use of an ancient (or Vedic) mathematical approach for building an ALU. Validation for the low power operation of the circuit is made by designing a conventional CMOS counterpart whose power is compared with our ancient arithmetic design. A 4x4 multiplier based on the Vedic and Conventional methods have been designed using SPICE simulator. Simulation results depict the Vedic design incurring 29% of reduced average power. © 2011 IEEE.

V S Kanchana   Bhaaskaran

Electronics

School of Electronics Engineering

Chennai Campus

Jayaprakasan V

Vijayakumar S

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Evaluation of the Conventional vs. Ancient Computation Methodology for Energy Efficient Arithmetic Architecture

2011 International Conference on Process Automation, Control and Computing

Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of partial product addition by using binary adders is proposed in this paper. The binary counters for varying bit count values are derived by modifying the basic 4:2 compressor circuit. A [Formula: see text] bit multiplier has been developed to validate the proposed computation method. This logic structure demonstrates lower power operation, reduced device count and lesser delay in comparison against the conventional Wallace tree multiplier structure found in the literature. The BCM implementation realizes 29.17% reduction in the device count, 66% reduction in the delay and 70% reduction in the power dissipation. Furthermore, it realizes 90% reduction in the power delay product (PDP) in comparison against the Wallace tree structure. The multiplier circuits have been implemented and the validation of results has been carried out using Cadence[Formula: see text] EDA tool. Forty five nanometer technology files have been employed for the designs and exhaustive SPICE simulations.

Journal of Circuits, Systems and Computers

Low Power, High Speed and Area Efficient Binary Count Multiplier

Multiplier is one of the primary hardware blocks in modern day digital signal processing (DSP) and communication systems. It is extensively used in DSP and image processing applications such as, Fast Fourier Transform (FFT), convolution, correlation, filtering and in ALU of microprocessors. Therefore, high speed, low area and power efficient multiplier design remain the critical factors for the overall system. This paper presents high performance and energy efficient implementation of the binary multiplier. The design is based on ancient Indian Vedic multiplication process and the low power energy recovery (aka adiabatic logic). The generation of partial sums and products in a single step in the Vedic approach and the energy recovery capability of the adiabatic logic together realize high speed and low power operation of the design. A 16X16 Vedic multiplier and conventional array multiplier based on the Differential Cascode Pre-resolve Adiabatic Logic (DCPAL) is proposed in the paper. Simulation results validate this design incurring 87.21 percent lesser power than the standard CMOS equivalent design. © 2014 IEEE.

2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

Low power vedic multiplier using energy recovery logic

Binary multiplier is one of the most time and power consuming architectures in an ALU. The performance efficiency of complex computations is determined by the multiplier algorithm used. Design of an efficient multiplier thus becomes important. An attempt has been made to implement an efficient multiplier using ancient computational techniques using charge recovery logic. This circuit is compared against the existing vedic multiplier circuits designed using conventional CMOS logic, to validate our claim. A 4 x 4 vedic multiplier using 2 N-2P type of charge recovery logic structure is implemented. The design and verification have been done using industry standard SPICE tools. The simulation results depict reduction in the average power consumption by 77.66 %. © 2013 Springer.

Lecture Notes in Electrical Engineering Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013)

Design and Implementation of an Efficient Multiplier Using Vedic Mathematics and Charge Recovery Logic

Low Power Digital CMOS Design

Tourism Management

Developing tourism destinations

Proceedings Eleventh International Conference on VLSI Design

Broadband U-NII wireless data

Proceedings International Conference on Computer Design VLSI in Computers and Processors

A universal Pezaris array multiplier generator for SRAM-based FPGAs

Journal	Data powered by Typeset2011 International Conference on Process Automation, Control and Computing
Publisher	Data powered by TypesetIEEE
Open Access	No