Wide bandgap and resulting low intrinsic carrier concentration enable longer charge retention time and high-temperature operation of Silicon carbide (SiC) flash memory devices. However, charge leakage through gate oxide reduces memory retention time and reliability of gate dielectric. Knowledge of conduction mechanisms of gate leakage current is essential for the optimization of process conditions to reduce leakage current and determination of suitable operating voltage of flash memory devices. In this work, conduction mechanisms contributing to gate leakage current in SiC MIS capacitors with different gate dielectric are extracted for the entire range of the gate electric field. Space charge limited (SCL) conduction mechanisms either Ohm’s law or trap filled limit process or combination of both are observed to be dominant at the low electric field. Hopping conduction found to be dominating the leakage current when the slope of leakage current changes from the lower value to a higher value. The sequence of mechanisms contributing to gate leakage current from low electric field to high electric field is found to be same in SiO2 annealed in O2 and N2, SiON and Al2O3/SiON stack. The trap filled limit process, trap-assisted tunneling and FN tunneling are dominating the gate leakage current at low, mid and high electric field respectively in all the investigated MIS capacitors. © 2019, © 2019 IETE.