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FFT implementation using floating point fused multiplier with four term adder
Published in IEEE
Volume: 2017-January
Pages: 1 - 6
Hardware realization of fast Fourier transform (FFT) function consists of multiple complex arithmetic operations. Floating point implementation of FFT provides wider dynamic range than their fixed point counterparts and fusing the floating point arithmetic operations inside the Butterfly unit of FFT improves the speed of operation. This paper presents an FFT implementation using a fused four term adder multiplier (FFAM) technique. The proposed FFT with FFAM is area efficient and operates at higher frequency. Radix-4 decimation in time butterfly FFT unit is designed and synthesized in Cadence using 180nm technologies with standard cell libraries. Based on the results it is analyzed that FFT with FFAM is 46% area efficient. The non-pipelined conventional architecture of FFT operates on 6MHz whereas proposed FFT architecture operates on 10MHz frequency. © 2017 IEEE.
About the journal
JournalData powered by Typeset2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)
PublisherData powered by TypesetIEEE
Open Access0