FIR filter is significant unit in digital signal processing (DSP). In this paper a reconfigurable architecture named as modified constant shift method (MCSM) is proposed. The architecture uses the concept of compressors to make the FIR filter more power efficient. This compressor based adder-tree architecture is capable of working for different word lengths of FIR filter coefficient with less hardware complexity. A three bit binary common sub expression elimination (BCSE) method is used to reduce the redundant expression in coefficient multipliers. The proposed architecture has been tested and verified on a Cyclone IV E EP4CE115429C7 FPGA. The result shows that the proposed compressor based adder-tree FIR architecture offers power reduction, with satisfactory area and speed compared to the existing CSM architecture. © 2017 IEEE.