Data hiding in one of the easiest technique to authenticate and resolve the copyright issues of multimedia data. This paper proposes a new VLSI architecture for data hiding in grayscale images using neighbour mean image interpolation technique, as this mechanism will have a minimum computation complexity. In this VLSI based data hiding process the secret digital signature is hidden in the host image and analyzed with the PSNR value and Payload capacity. © 2015 IEEE.

Sakthivel S M

Electronics

School of Electronics Engineering

Chennai Campus

Ravi Sankar A

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

FPGA implementation of data hididng in grayscale imagesusing neighbour mean interpolation

2015 2nd International Conference on Electronics and Communication Systems (ICECS)

Background: The rapid advancement of multimedia technology has made the data communication and data sharing so comfortable through wireless network and Internet. During this multimedia communication, the piracy of the multimedia content is a primary concern (i.e. anyone can duplicate or alter the originality). One of the most efficient techniques to protect the multimedia data is watermarking. It is the process of adding a secret digital signature to the host content in a visible or invisible form. The process of watermarking will be of reversible or irreversible nature. Method: In this paper, a reversible watermarking strategy using prediction technique with its hardware architecture is proposed. In the VLSI implementation aspect three different architectural structures are proposed as pipelined, parallel and dataflow architecture with embedding concept. Findings: Finally, all the three architectural designs are modelled and implemented using Verilog HDL. The entire process is integrated in a specific chip. Application: It can be used as a separate co-processor for carrying out the watermarking in real time with any multimedia devices. © Springer Nature Singapore Pte Ltd. 2018.

Lecture Notes in Electrical Engineering VLSI Design: Circuits, Systems and Applications

Pipelined and Parallel Architecture of Reversible Watermarking for Greyscale Images

Microelectronics Journal

FPGA and ASIC implementation of robust invisible binary image watermarking algorithm using connectivity preserving criteria

Journal	Data powered by Typeset2015 2nd International Conference on Electronics and Communication Systems (ICECS)
Publisher	Data powered by TypesetIEEE
Open Access	0