There has been many implementation of the serial Fast Fourier Transform (FFT) operation. In the most cases, output of the serial FFT block is in bit reversed order, so it need a reordering block to reorder the output. However some of the FFT application does not require the ordered output of FFT, such like spectral subtraction method. In the paper, we represent a FPGA implementation of the serial FFT and IFFT architecture in one block without reordering the block. The design is simulated using Modelsim simulator. Our 8 point FFT /IFFT blocks utilizes 16102 logic elements on the chip i.e. 24% of the available logic blocks. The block can work in maximum frequency of 12.56 MHz. © 2015 IEEE.