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Fully pipelined high speed SB and MC of AES based on FPGA
, J. Jean Jenifer Nesam
Published in
2013
Volume: 5
   
Issue: 4
Pages: 3184 - 3190
Abstract
A new implementation scheme of high speed mixcolumn based on sharing the use of sbox is introduced in this paper. The single MC (mixcolumn) shares the single SB(sbox-subbyte) based on the time slot. For each time slot SB and MC performed parallelly. Earlier they use 16 individual sbox for each input. In our paper, we introduce sharing concept of sbox which can eliminate the use of 16 individual sbox and reduce the delay and cost. Normal AES uses shiftrows followed by sbox needs 128 bit for their operations that consumes large time. By eliminating shiftrows, we can increase the speed of the AES operation. LUT based sbox consumes more than 75% of power. In our paper we design the Composite field sbox which reduces the power consumption of AES architecture. Sbox is the main source of information leakage since the values are fixed one. In our paper the values of sbox are masked by using particular fixed value thus increase the system security.
About the journal
JournalInternational Journal of Engineering and Technology
ISSN23198613