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Proceedings Article
Functional verification of the Axi2OCP bridge using system verilog and effective bus utilization calculation for AMBA AXI 3.0 protocolPublished in IEEE
2015
Verification is the process of exploring the correct functioning of the design. It is not possible to guarantee a design without proper verification, because misunderstanding and misinterpretation of the specifications, incorrect interaction between the cores and IPS leads to unexpected behavior of the system. Functional verification plays a key role in validating a design and its Functionality. AXI2OCP Bridge connects two different protocols i.e. advanced extensible interface and open core protocol. AXI2OCP Bridge helps in converting AXI 3.0 format signals to OCP format signals, AXI address to OCP address and AXI data to OCP data. Protocols With effective Bus utilization leads to have a faster data rate with increased performance. Measuring the Bus utilization parameter for the AXI 3.0 protocols generated test cases and functional verification of the AXI2OCP Bridge using system verilog language is the main idea of this paper. © 2015 IEEE.
Topics: Functional verification (62)%62% related to the paper and Verilog (55)%55% related to the paper
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About the journal
| Journal | Data powered by Typeset2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS) |
|---|---|
| Publisher | Data powered by TypesetIEEE |
| Open Access | No |
Authors (2)
Mahesh Ganesapillai- Functional verification of the Axi2OCP bridge using system verilog and effective bus utilization calculation for AMBA AXI 3.0 protocol
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