This paper proposes the design of incorporating fine grain and coarse grain gating techniques for the SRAM cell and SRAM array respectively. Independent gate FinFET, tied gate FinFET and independent gate FinFET with pass gate feedback are employed for power gating the 6T SRAM cell. The leakage power, stability (SNM) and delay comparisons have been made. The simulations are carried out using Cadence® Virtuoso tools, employing the 32nm Predictive Technology Model (PTM) files for the MOS devices and 32nm BPTM files for the FinFETs. The results validate the advantage of using power gating for reduced static power dissipation. The independent gate FinFET based 6T SRAM cell using pass gate feedback incurs 2.23uW of power during the hold operation, as against the comparatively negligible power dissipation of 27.67pW with the power gating. © 2015 IEEE.