A software model of hardware estimator is developed. The behavioral description is transformed into an intermediate format called Control Flow Graph (CFG). The graph is partitioned into hardware and software. The unoptimized hardware in intermediate graph is estimated by transforming the graph into matrix format. The partitioned hardware of Control Flow Graph is translated as behavioral network graph. The High Level Synthesis and Logic Synthesis are performed using the BNG with simple logical transformation. The final RTL obtained from the conventional synthesis method and BNG method for resource and timing constraint were presented. The cost estimation for the various control construction is being tabulated. © 2007 IEEE.