Finite Impulse Response (FIR) filters is very important in signal Processing Applications. This research is to analyze the performance of FIR filter with the Xilinx Software. The Distributed Arithmetic (DA) algorithm is extensively used in FIR Filter to improve its speed and reducing the area of the filter. The design of low power filter will be achieved by pipelining and parallel processing concept on distributed Arithmetic. The aim is to design filter which has less delay time and supports the pipelining/parallel processing feature, helps in high speed with less power dissipation and area. The paper discusses FPGA implementation of FIR filter and due to parallel data processing its computation is fast and also provides an efficient architecture in terms of area and power consumption. New Distributed Arithmetic is a high performance and for low power filter.