ASIC implementation of convolution plays a pivotal role in digital signal processing and analysis. One of the factors in performance evaluation of any system is its speed. In this paper, direct method of computing the discrete linear convolution of finite length sequences was used in order to speed up the process. Convolution related functions such as cross-correlation and auto-correlation were also implemented. Multipliers are the building blocks of a convolution system. Since they dominate most of the execution time, for optimizing the speed, 4×4 bit Vedic multipliers based on 'Urdhva- Tiryagbhyam' (UT) sutra was used. The Verilog HDL coding for the proposed design was done and implemented using Cadence RTL complier with standard 90nm CMOS technology and the results were compared with other conventional methodologies. © 2006-2015 Asian Research Publishing Network (ARPN).