Jayakrishnan P

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Niyas R.M

Maillikarjun K.H.

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN)

Video coding is used for lot of multimedia purposes like video conferencing, digital storage media, Internet streaming and television broadcasting. This paper presents a new design for the implementation of Full-Search (FS) Variable Block Size (VBS) Motion Estimation (ME), which is a key issue of different video compression standards such as MPEG-1, MPEG-2, MPEG-4 Visual, H.261, H.263 and H.264. The FS algorithm is widely used for implementation of ME in video compression algorithms. This design is fully parametric in terms of block size, which is variable, and the Sum of Absolute Differences (SAD) is presented by re-using the outputs. The design features high efficiency in terms of operating frequency and reduction in hardware complexity. These architectures are designed using Verilog Hardware Description Language (HDL) and the functionalities are verified using ModelSim Simulator. For two different designs, namely 1-D and 2-D systolic architectures are analyzed in terms of frequency, gate count, total power. The design is synthesized using CADENCE RTL compiler with TSMC 90nm standard cell library. The operating frequency of 1-D design is 323.20 MHz and 2-D design is 166.67 MHz and the gate count for 1-D is around 5k and for 2-D is around 21k gates and these designs can treat up to 41 Motion Vectors. © 2014 IEEE.

International Conference on Circuits, Communication, Control and Computing

2-Dimensional systolic architecture for H.264/AVC variable block size motion estimation

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC

IET Circuits, Devices & Systems

Very large scale integration (VLSI) implementation of low-complexity variable block size motion estimation for H.264/AVC coding

IEEE Transactions on Consumer Electronics

An efficient VLSI architecture for H.264 variable block size motion estimation

Information technology. Generic coding of moving pictures and associated audio information

High speed architecture for Variable Block Size Motion Estimation in H.264

Journal	Data powered by Typeset2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN)
Publisher	Data powered by TypesetIEEE
Open Access	0