Hummingbird algorithm is one of the recently proposed light weight cryptographic algorithms targeted for resource constrained devices like RFID (radio frequency identification), smart cards and majority of wireless sensor nodes. The main advantage of this algorithm is that it provides adequate security with smaller block size. As per the previous works on this algorithm, area and performance are two main design tradeoff of this algorithm. Performance is increased by loop unrolling and area is optimized by looping. So optimization in both area and performance is a big challenge. This work, proposes efficient hardware architecture for the hummingbird algorithm using partial loop unrolling which concerns both the area and performance of hardware implementation. The overall architecture was modeled using verilog HDL and synthesized using cadence RTL compiler with 45nm Technology from TSMC. Proposed design also implemented in low cost Spartan 3 FPGA board and the results are compared with the existing implementations. Results show that there is an area reduction of around 6% andthroughput almost get doubles. © 2015, International Institute for General Systems Studies. All rights reserved.