High efficiency video coding (HEVC) is the latest video coding standard developed by ITU-T in 2013 for better performance with lower bit rate. It supports variable block sizes ranging from 64×64 to 8×8. In this paper, we propose architecture for high throughput fractional motion estimation for HEVC video coding. The design has two stages, first stage to perform interpolation and second stage is based on systolic array with 16 processing element to compute the sum of absolute differences (SAD). The systolic array will be able to process 16 pels per clock cycle. It is observed that video frames in CIF, 720p, and 1080p formats are processed on an average of 108,363, 1,206,035 and 2,514,864 clock cycles respectively using the proposed hardware. Also, the average PSNR’s of the CIF, 720p, and 1080p format videos are also observed to be 30.79dB, 32.87dB and 34.1426 dB respectively. The proposed hardware is coded using verilog and synthesised in TSMC 90 nm. © 2019, Institute of Advanced Scientific Research, Inc.. All rights reserved.