This paper provides an efficient VLSI architecture to increase the throughput and security of the Advanced Encryption Standard (AES) Algorithm. The existing architecture provide the Look up Table technique for the Subbytes and inverse Subbytes transformation used in AES algorithm, our proposed technique uses combinational circuit and pipelining technique which increase the throughput and reduce the delay. This design proposes a new technique for implementing the S-box, which decides the speed and power of AES architecture and the basic components of this architecture is made completely fault detectable by using pseudo-nMOS technology and thereby increases the security of this system. This AES design was modeled using Verilog HDL and synthesized using TSMC's 90 nm standard cell library with RTL Compiler, and physical design implementation was done using SOC Encounter and thereby achieved a through put of 58.18 Gbps after detailed routing. The basic security of the system is validated by using Cadence Virtuoso in the transistor level design. © 2012 IEEE.