The Negative Bias Temperature Instability (NBTI) is one of the serious reliability issues of the p-type MOS based transistors. The downscaling of gate oxide thickness to reestablish the gate voltage controllability over the channel adversely affects the reliability of the devices and circuits. The multigate transistors such as FinFET which shows superior device scalability over the planar MOSFET are also severely affected by the NBTI effects in the nanoscale regime. The time to digital converter (TDC) is a signal conditioning circuit which is used to convert the specified time interval between two events into the digital codes. The proper functioning of the TDC is based on accuracy of the propagation delay of its designed delay lines. The degradation of the delay in the delay lines due to NBTI lead to improper code conversions. The Vernier delay line TDC is designed using the 30 nm Triple Gate FinFET technology with high resolution of 10 ps. The effect of NBTI degradation over the FinFET based Vernier delay line TDC in the critical nodes is analyzed. The occurrence of offset error, increase in the non linearity and degradation of resolution are observed due to the NBTI degradation. © 2017 IEEE.