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Implementation of BIST using self-checking circuits for multipliers
Padharpurkar N.G,
Published in IEEE
This paper presents the architectural design of Built In Self-Test (BIST) using self-checking circuits for bit-array multipliers including standard bit array multipliers and multipliers based on booth algorithm. The architecture of BIST depends on area efficient self-checking full adder due to which fault detection and recovery of detected faults is ensured on the same silicon area. Self-checking full adders are inserted within the multiplier design so that fault detection and recovery can be done at any intermediate stage of an array multiplication. Simulation results shows that implementation of this self-checking mechanism into carry save adder design and array multiplier design reduces the area overhead by 25%-30% as compared to previous testing circuits for multipliers. Simulation results show that BIST with self-checking testing technique can bear up to six transient faults with optimum 70% probability of error detection, which is considerably higher than DMR and TMR technique. © 2015 IEEE.
About the journal
JournalData powered by Typeset2015 International Conference on Computer, Communication and Control (IC4)
PublisherData powered by TypesetIEEE
Open Access0