A Viterbi decoder uses the Viterbi algorithm for decoding a bit stream that has been encoded using Forward error correction based on a Convolutional code. The maximum likelihood detection of a digital stream is possible by Viterbi algorithm. In this paper, we present a Convolutional encoder and Viterbi decoder with a constraint length of 7 and code rate of 1/2. This is realized using Verilog HDL. It is simulated and synthesized using Modelsim PE 10.0e and Xilinx 12.4i. © 2011 IEEE.

V S Kanchana   Bhaaskaran

Electronics

School of Electronics Engineering

Chennai Campus

V. Kavinilavu

S. Salivahanan

S. Sakthikumaran

B. Brindha

C. Vinoth

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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Implementation of Convolutional encoder and Viterbi decoder using Verilog HDL

ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology

Implementation of convolutional encoder and Viterbi decoder using Verilog HDL