This paper presents an implementation of Hierarchical DFT approach to get better testability i.e. more test coverage at block level. The SOC is divided into number of Layout regions and layout as well as DFT regions as per the functionality requirement. The well-proven D-algorithm technique is considered for ATPG purpose. The Vectors are generated at the DF level inside the chip using Modus tool from Cadence at 16nm technology. For DFT region in the SOC, patterns are targeted for different test modes which includes both stuck-at and transition fault coverage. Each and every DFT region is targeted for Stuck-at and transition fault coverage of greater than 99% and 85% respectively. Before applying these patterns on the real silicon (chip) in the ATE (Automatic Test Equipment), they are validated by Simulation using IES from cadence at both block and device level. At block level the patterns are validated with and without timing constraints. The timing constrained simulation occurs by annotating the design netlist w.r.t. STA related timing reports, called as SDC constraints. Further, the block level DFT region pins are mapped to the corresponding device level pins. The patterns generated at block level being mapped to device level are again validated by logical simulation for the proper top mapping connections.