Design of a low power 32 bit MAC unit using adaptive power control (APC) system is proposed in this paper. Since many of the digital signals processing (DSP) application require MAC, power reduction in the same would be quite beneficial. The problems concerned with power gated digital circuitries are: energy overhead, degradation of speed, loss of information and power or ground noise. To overcome these difficulties APC system is employed. APC system manipulates the speed controllability of the power gating devices. It identifies and optimises the utilization of unused slack. Apart from APC, power reduction is also observed by inculcating optimal low power techniques to design the MAC unit. The 32 bit MAC implemented includes Vedic multiplier using urdhva tiryagbhayam algorithm and a 64 bit carry save adder, which reduce power, area and propagation delay considerably. The complete system is implemented using standard CMOS 45nm technology. © Research India Publications.