Reversible quantum logic plays an important role in quantum computing. This paper proposes implementation of MAC unit using reversible logic. We have discussed all the elementary reversible logic gates which are used in the design. Here, 4 × 4 irreversible MAC has been compared with reversible MAC and it has been found that, there is 25.6% reduction in the power consumption. The design has been simulated using ModelSim and synthesized using Cadence RTL compiler. © Springer India 2016.

Dhanabal R

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Bharathi V.

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Implementation of MAC Unit Using Reversible Logic

Proceedings of the International Conference on Soft Computing Systems Advances in Intelligent Systems and Computing

This paper presents the design and implementation of 16-bit floating point RNS Multiply and Accumulate (MAC) unit. Residue Number System (RNS) gained popularity in the implementation of fast arithmetic and fault-tolerant computing applications. Its attractive properties such as parallelism and carry free computation have speed up the arithmetic computations. Floating Point can be represented as M×BE where M is Mantissa, E is the Exponent and B is the Base. The MAC unit consists of three units - Floating-point multiplier, Conversion unit and an Accumulator. The floating-point multiplier makes use of Brickell's Algorithm, the conversion unit makes use of a parallel conversion for the forward conversion and the Chinese Remainder Theorem for reverse conversion and the accumulator includes an adder unit which can make use of any of the conventional adders that depends on the moduli of the RNS being used. The input takes form of half-precision format where there is 1-bit for sign, 5-bits for exponent and 10-bits for mantissa. The design is coded in Verilog HDL and the synthesis is done using Cadence RTL Compiler. © 2014 IEEE.

2014 International Conference on Reliability Optimization and Information Technology (ICROIT)

Implementation of floating point MAC using Residue Number System

This paper proposes implementation of IEEE floating point (FP) multiplication and division. Arithmetic on IEEE FP numbers imposes more challenges compared to fixed-point arithmetic. These particularly include the simultaneous computation of normalization and rounding. We show the efficient way of solving these challenges for the implementation of floating point (FP) addition and multiplication. The proposed designs aim at reducing power dissipation. Here multi threshold voltage technique is used for reducing power dissipation. The proposed implementations are according to the IEEE 754 FP standard. © Research India Publications.

2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE)

Design and implementation of low power floating point arithmetic unit

2012 International Conference on Communication, Information & Computing Technology (ICCICT)

Reversible implementation of novel multiply accumulate (MAC) unit

ACM Journal on Emerging Technologies in Computing Systems

Reversible logic synthesis with Fredkin and Peres gates

Journal	Data powered by TypesetProceedings of the International Conference on Soft Computing Systems Advances in Intelligent Systems and Computing
Publisher	Data powered by TypesetSpringer India
ISSN	2194-5357
Open Access	No