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Proceedings Article
Implementation of non-linear pipelined floating point adderPublished in IEEE
2013
Topics: Double-precision floating-point format (62)%62% related to the paper, Adder (62)%62% related to the paper, IEEE floating point (61)%61% related to the paper, Floating point (58)%58% related to the paper and Half-precision floating-point format (56)%56% related to the paper
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About the journal
| Journal | Data powered by Typeset2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE) |
|---|---|
| Publisher | Data powered by TypesetIEEE |
| Open Access | 0 |
Authors (1)
Jayakrishnan P- 2-Dimensional systolic architecture for H.264/AVC variable block size motion estimation
- Implementation of non-linear pipelined floating point adder
- Implementation of adder structure with fast carry network for high speed processor
- Implementation of pipelined Booth Encoded Wallace tree Multiplier architecture
