The Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) play a vital role in signal processing. It is often used in many communication systems. This paper realize a 16-bit FFT architecture using radix-4 algorithm. The radix-4 structure can be used when the length of the signal is in the powers of 4. The two main challenges of this work is the complex arithmetic operations, floating point addition and multiplication operations. As we require floating point operations we went for floating point adders and multipliers. The complex multiplier is the most power consuming block in the FFT processor. The proposed Radix-4 FFT processor is realized on Verilog platform using vertex FPGA. © 2015 IEEE.

Nithin Battula

Department of Automotive Engineering

School of Mechanical Engineering

Vellore Campus

Sivanantham S

Department of Micro and Nanoelectronics

School of Electronics Engineering

Sivasankaran K

Niharika S

Sali A.S

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Implementation of radix-4 butterfly structure to prevent arithmetic overflow

2015 Online International Conference on Green Engineering and Technologies (IC-GET)

Background: Floating Point (FP) multiplication has found its importance in many microprocessors but it is very difficult to implement on FPGA because of its complicated internal computation. Methods: We investigate partial product (PP) reduced FP multiplication based on Radix-4 Booth Encoded Algorithm (BEA). Radix-4 BEA reduces the number of PP generation by half. PP reduction performed in three steps such as Grouping bits (3-bit for each group), Encode the group and PP calculation for each group. Findings: The investigation results show that Radix-4 BEA works perfectly on signed multiplication and unsigned (FP mantissa) multiplication needs some extra consideration. Radix-4 BEA grouping multiplier bits need overlapping one bit from both adjacent group that limits block and parallel processing. 2's complement calculation and sign extension essential for PP generation that increases the resource utilization. In this paper, 32 bit improved FP multiplication based on classical recoding and parallel processing method is proposed. Classical recoding reduces PP generation by half without overlapping, sign extension and 2's complement. 24 bit mantissa split into blocks (8 bit each) and each block is recoded using classical recoding algorithm and all blocks are performed in parallel. Applications: The experimental results show that our proposed design runs with high frequency with less resource utilization and suitable for signal processing applications.

Fulltext

Indian Journal of Science and Technology

An Efficient Single Precision Floating Point Multiplier Architecture based on Classical Recoding Algorithm

Objectives: This paper aims at designing high speed and high throughput Fast Fourier Transform (FFT) processor which is a critical block and is widely used in many Digital Signal Processing applications. Methods: The proposed model works with both real and complex type of input data. Pipelining in the proposed architecture is achieved with single delay feedback methodology. Findings: The CMOS 0.18 μm is used to design Application Specific Integrated Circuit (ASIC) for the proposed FFT processor and it works with an input size of 36 bits at the operating frequency of 100 MHz, occupies an area of 1.27 mm and consumes 39 mW, at an operating voltage of 1.8V.Obtained results are compared with existing methods in terms of input word length, throughput, power dissipation and it shows that the proposed architecture gives high throughput, uses 3x more word length and 2x less power dissipation. Applications: The designed chip can be used in scientific computations since it require less power and operates in high speed.

ASIC Implementation of High throughput FFT Processor for Scientific Applications

IEEE Transactions on Circuits and Systems I: Regular Papers

Multimode Memory-Based FFT Processor for Wireless Display FD-OCT Medical Systems

Journal	Data powered by Typeset2015 Online International Conference on Green Engineering and Technologies (IC-GET)
Publisher	Data powered by TypesetIEEE
Open Access	0