This research work presents the application-specific integrated circuit (ASIC) implementation of one dimensional (1 × 8) and two dimensional (8 × 8) discrete cosine transform using the reversible logic gates. During the DCT implementation, the integer DCT method of realization is adopted, thereby eliminating the occurrence of floating-point operations in the data path architecture. Thus, the integer mode of DCT realization using reversible logic gates in the proposed DCT architecture improves the delay, power and area of the 1D and 2D DCT data path structure when compared with the normal real DCT implementation. The proposed methodology of DCT implementation includes the construction of full adder and full subtractor using reversible gates and then extended for the realization of the DCT butterfly structure. Especially in this research method, Peres reversible gate is used for the implementation of full-adder and Thapliyal Ranganathan (TR) gate for the implementation of full subtractor, respectively. Thus, the 1D and 2D DCT implementation using reversible logic gates in 180nm technology nodes consume an overall area of 55504.311 sq.µm and 1122324.044 sq.µm respectively. © 2021 Institute of Physics Publishing. All rights reserved.