Background/Objectives: In the contemporary era, due to the rapid development in various low power VLSI circuits, the primary factors that affect the performance of the circuits are gaining much importance. The static random access memory (SRAM) is one of the significant circuits employed in low power VLSI systems. Many researchers continue focusing on efficient SRAM designs and towards increasing the stability of the SRAM cells. Generally, single-bit line SRAM cells are more stable than the dual bit-line SRAM cells. The stability of SRAM cells depends on certain factors, such as control over the word line voltage, leakage power and power dissipation during read/write operation. Nowadays, several low power techniques have been developed for increasing the stability of SRAM cells. One such a technique is the non-conventional method called as adiabatic or energy recovery technique. Application of this adiabatic technique in the operation of an SRAM cell can enhance the read noise margin, since it determines the stability of the SRAM cell. This adiabatic technique mainly works on the focus that the adiabatic logic circuits consume less power, conserves energy and reutilizes the charge from the circuit nodes. This paper also proposes a new SRAM cell which shows improvement in read noise margin. Methods/Statistical analysis: Cadence EDA tools have been employed for the simulations. Layouts of different SRAM cells have been made using 180nm and 45nm CMOS technology library. Read and write operation output, power calculation and read noise margin calculations are performed with the help of the cadence virtuoso tool. For calculating read noise margin, input-output characteristics graph of two cross coupled inverters are plotted, and the maximum value of the square in the graph provide the value for the read noise margin. Furthermore, comparisons of conventional SRAM cells with the proposed SRAM cell are discussed in terms of power dissipation and read-noise margin. Conclusion/improvement: The results of the proposed SRAM cell are compared with the conventional SRAM cells. The overall power consumption of the proposed SRAM cell is 1.061E-3 watt and the value of the read noise margin is 0.115. On the other hand, the conventional 6T SRAM cell incur overall power consumption of 1.033E-3 watt with the read noise-margin of 0.121. The power dissipation of the proposed circuit is reduced by 3.1% when compared with the conventional 6T SRAM cell. Further, the proposed SRAM cell architecture has 52.17% better read noise margin when compared with the existing techniques. © 2017 IEEE.