In this manuscript, the impact of dielectric pocket on analog/radio-frequency (RF) performances of SOI-TFET is investigated. The inclusion of a dielectric pocket to SOI-TFET has been found to have great potential in eliminating the ambipolarity when Tunnel FET is biased at a higher negative gate voltage. With 2-D numerical simulations, it is demonstrated that inclusion of a dielectric pocket on partially scaled drain region improves the analog/RF performances of SOI-TFET such as gate-to-drain capacitance, output resistance, gain-bandwidth product and cut-off frequency. Furthermore, it is shown that a high-k dielectric pocket (HfO2) provides more reduction in ambipolar conduction compared to a low-k dielectric pocket (SiO2). But, analog/RF performance parameters are observed superior in SOI-TFET with low-k dielectric pocket compared to conventional and high-k dielectric pocket SOI-TFET. Additionally, to demonstrate the advantage of using a dielectric pocket to SOI-TFET in circuit applications, we compare the transient response of conventional SOI-TFET with low and high-k dielectric pocket SOI TFET. © 2020 Informa UK Limited, trading as Taylor & Francis Group.