Layout is an important step towards Integrated Circuit(IC) designing. The following research work focuses on the techniques that can be applied on layout to optimise the digital IC. The work discusses about other methods as well that are proposed to optimise ICs. However, this research work shows a step-by-step approach in implementing Euler’s Path and Minimum Distance Rule. It targets the change in the switching power, layout area and delay in the circuit to show the effect of the proposed methods. Euler’s Path and Minimum Distance Rule are the two techniques that are used on an example circuitry that implements (AB+CD)' Boolean expression. Cadence Virtuoso simulation tool is used for simulations and quantitatively analyse the mentioned parameters. Post layout simulations are used to get more realistic results because it takes parasitic elements into account as well. The results from layouts with and without the above techniques applied, is compared, showing a decrease in switching power, delay and layout area for the circuit with the optimization techniques. The results in this work show that with improvement in layouts of digital ICs, we can make ICs more reliable. More complex circuitry will benefit from these techniques because they will need lesser layout area which will aid in adding more circuitry and increasing the complexity further more. © BEIESP.