Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-μm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA. © 2010 IEEE.

Ramkumar T

Department of Computer Applications

School of Information Technology and Engineering

Vellore Campus

Kittur Harish Mallikarjun

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

2018 2nd International Conference on Micro-Electronics and Telecommunication Engineering (ICMETE)

Design and Implementation of Dual-Pair-Single-Rail Checker with Carry Select Adder

This paper focuses on the design of self-checking carry select adder (CSTA) using FinFET devices. The CSTA adder comprises of Boolean to Excess-1 converter and D-latch. While going for multi-bit addition, it is more prone to various types of faults. Hence, the design of a self-checking CSTA is more prone to faults. This paper focuses on the design of 4-bit CSTA using FinFET and a sum bit checker design using FinFETs. The simulations are carried out using Cadence® Virtuoso platform with 32-nm FinFET technology library. The results demonstrate a device overhead of 12 and slight increase in delay and power consumption. However, the purpose of the carry checker design has a great impact on preventing the propagation of faults and ultimately ends in fault-free circuit. © Springer Nature Singapore Pte Ltd. 2018.

Lecture Notes in Electrical Engineering VLSI Design: Circuits, Systems and Applications

Design and Implementation of Multi-bit Self-checking Carry Select Adder

High-performance and low-power are the two main criteria in modern digital design. Based on the idea of sharing two adders used in the Carry Select Adder (CSA), a new design of a low-power high performance adder is presented. The new adder is faster than a Ripple Carry Adder (RCA), but slower than a CSA. On the other hand, its area and power dissipation are smaller than those of a CSA. © Research India Publications.

2017 International conference of Electronics, Communication and Aerospace Technology (ICECA)

Low power high performance carry select adder

Background/Objectives: XOR gate is a primary element in binary adders because which is used to detect sum - output. Inthis paper a 2-input XOR gate is accomplished by a modified design. Methods/Statistical Analysis: Usually a Half Adder(HA) circuit is designed with one XOR and one AND gate but if this modified XOR is used in HA, the design requires onlyone XOR gate and the AND gate can be acquired from XOR gate itself. Findings: This modified XOR gate design gives betterresult when the adder circuit has more number of XOR gates, so we used this modified XOR gate in conventional sqrt CSLA,Binary to Excess-1 Converter (BEC) based sqrt CSLA and Optimized Logic Based (OLB) sqrt CSLA. The results show thatArea - Delay - Product (ADP) has been reduced in proposed circuits, 12.45% in conventional sqrt CSLA, 21.45% in BECbased sqrt CSLA and 17.81% in OLB sqrt CSLA. Applications/Improvements: These adders can be used in ArithmeticLogic Unit (ALU) of a micro-processor as a binary adder.

Fulltext

Indian Journal of Science and Technology

Low - Power and Area - Efficient Square – Root Carry Select Adders using Modified XOR Gate

Multiplication is one of the major fundamental operations and key hardware blocks in any digital system. This paper presents the comparison of the VLSI design of uniform carry select adder (UCSLA)-based multiplier technique with the variable carry select adder (VCSLA)-based multiplier technique. The analysis is carried out on the different bit sized values of unsigned inputs, and output results show that the area, power, and delay are reduced in the UCSLAbased multiplier technique compared to VCSLA-based technique. The timing delay in 64-bit VCSLA-based multiplier technique is 95.25 ns for performing the multiplication, which is reduced by 11.11% in the UCSLA-based multiplier technique. In the same manner, area is reduced by 39.42% and power also reduced by 19.28% in UCSLA-based multiplier technique. The simulation works of multipliers are carried out in Verilog-HDL (Modelsim). After the simulation, the results are obtained using cadence tool. © Springer India 2015.

Journal	Data powered by TypesetIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Publisher	Data powered by TypesetInstitute of Electrical and Electronics Engineers (IEEE)
ISSN	1063-8210
Open Access	0