Reconfigurability is the utmost requirement for Finite Impulse Response (FIR) filters that are used in many applications related to digital signal processing. The transposed form of filter often support multiplication techniques and they are pipelined which enhances the performance of the filter and also low power is often achieved. In this work, an LUT reduction technique is used for the blocked FIR filter, which greatly reduces the power consumed by the filter and also enhances the speed by reducing the delay of the circuit. A comparison is made for the proposed filter design with the existing blocked FIR filters presented over the years. The proposed design offers less Energy per sample (EPS) and Area delay product (ADP) when compared to the reconfigurable architectures for large filters. From the synthesis results, it can be seen that for a filter length of 16, the proposed design offers 34.6 % reduction in ADP and 63 % reduction in EPS. © BEIESP.