This paper presents an architecture for low power and low complexity implementation of a linear periodically time varying (LPTV) interpolation filter using thread decomposition (TD) technique which decomposes a filter into finite computational threads. TD technique enables us to develop the proposed architecture as a generalization to linear time invariant (LTI) filter structure. The area complexity of the proposed architecture is significantly reduced by optimizing the concurrent threads of the conventional design. Reduction of power consumption is achieved in the proposed design by eliminating futile multiplications and reducing the operating frequency of the multipliers. It involves nearly one fourth the number of adders, multipliers and delay elements compared to the conventional design. The proposed structure is implemented on Virtex FPGA 2vp30-7ff896. From the synthesis results, it is found that the proposed design offers 35.7% reduction in power consumption and 20.6% reduction in device utilization over the conventional design. © 2016 IEEE.