In VLSI system design, one of the most significant areas of on-going research is high speed with low power system design. Usually the speed of the VLSI circuits like binary adders can be improved by more parallelism but, this more parallelism idea will increase the power consumption and area of the circuit. Therefore there is a trade-off between speed and power/area. A carry select adder is one of the fast binary adders but it consumes more power and area. In this paper, we proposed a low power and area efficient and high speed binary carry select adder (CSLA). The half sum and carry generator (HSCG) of the proposed CSLA is designed with a new methodology, that the HSCG output are estimated using input A and B not with carry-in hence it is faster and results in less area leads to low power consumption. Moreover, the NAND gate based circuit is used to compute the intermediate carries within the block and carry-out of the block which are derived from HSCG output along with carry-in. Similarly, the full sum of the proposed adder is generated from XNOR gate based circuitry by utilizing the intermediate carries of the block. The existing and proposed CSLAs are synthesized with the Synopsys EDA tool using 32 nm CMOS technology. The performance of the existing and proposed designs are analyzed and the results shows that the proposed 64-bit CSLA exhibits average reduction of 43% in power and average of 25% less utilization in terms of area compared to existing design. This proposed CSLA is used in a FIR Filter and obtained significant reduction in ADP and PDP. © 2020, Springer-Verlag GmbH Germany, part of Springer Nature.