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Low power custom circuit building using standard cells with reduced leakage by applying gate length biasing technique for high end computing applications
, S. Kuppuswamy
Published in Asian Research Publishing Network
Volume: 13
Issue: 4
Pages: 1396 - 1401
In this paper the concept of leakage power reduction using Gate Length Biasing technique is used. All the CMOS instances used are gate length biased. This paper explains the leakage reduction in a digital circuit which makes use of gate length biased NAND gates to achieve lower power dissipation. All the designs and simulations have done using gpdk 90nm technology and verified using Cadence and Liberate tools. The motive of this paper is clearly indicated using a 8 bit Multiplier Accumulator unit (MAC). The MAC unit consists of several individual blocks: 8 bit multiplier, a 17 bit adder and a 17 bit accumulator. These blocks at various places make use of the modified NAND_GLB gate. These gates are placed away from the critical path. This is because any devices speed or swift working depends upon the delay that occurs in the critical path. So it's always better to keep the delay at the critical path very minimum. Thus the increased threshold devices or the modified devices are placed at other non-critical paths so that the leakage due to those cells is reduced. This path identification is done using an heuristic algorithm. This method thus helps in reducing the major issue of sub threshold leakage. This leakage is due to the direct connection from VDD to GND even when the device is not in use. The power variation that was observed in the MAC units with and without the GLB gates are compared and a reduction of 36% is obtained. © 2006-2018 Asian Research Publishing Network (ARPN).
About the journal
JournalARPN Journal of Engineering and Applied Sciences
PublisherAsian Research Publishing Network