Here, we are proposing a novel design of 2:4 decoder and 4:16 decoders which are designed by using line decoder concept. By using proposed design, the area and power consumption of 2:4 decoder and 4:16 decoder can be reduced. In the existing work they have used DVL (Dual Value Logic) and Transmission gate Logic to implement a 14-Transistor 2:4 decoder for minimizing the transistor count. By using 2:4 pre-decoders and post-decoders they implemented 4:16 decoders. Mixed logic is also used for this purpose. Here we have implemented a single 2:4 decoder with minimum transistor count and low power consumption which is used to design a 4:16 decoder. We implement the proposed design in Cadence Virtuoso simulation at 90nm technology and calculated the power and area.