Pre-scalar, this is considered as the most critical block in the design of frequency synthesis plays very important role, whenever we talk about high frequency operation. These blocks are used typically in PLLs for frequency synthesis. Rigorous experiments have proved that the major contribution for power dissipation in ADPLL is because of pre-scalar block. Hence it becomes very crucial to design the pre-scalar block with minimum power dissipation. In this paper we adopt a technique of using Power PC flip flop to design a divide by 16/17 pre-scalar, which consumes very minimum power. The propound circuit operates up to ∼1GHz consuming very less power of 0.749mW. The output frequency is in the range of 50MHz to 60MHz. Low power divide by 16/17 pre-scalar using Power PC flip flop is proposed at 0.12μm CMOS technology using BSIM4 model at a supply of 1.2V. The circuit is schematically verified in DSCH3.8. The layout verification was carried out in Microwind2. From the simulation it was observed that very minimum power dissipation was obtained with a minimum surface area of 1875.9μm2. © 2017 IEEE.