Divider is an inevitable and basic hardware module employed in advanced and high speed digital signal processing (DSP) units of high precision. It is widely used in radar technology, communication, industrial control systems and linear predictive coding (LPC) algorithms in speech processing. This paper proposes a fast, low power and cost effective architecture of a divider using the ancient Indian Vedic division algorithm. The merits of the proposed architecture are proved by comparing the gate count, power consumption and delay against the conventional divider architectures. The validation of the proposed architecture has resulted in 52.93 percent reduction in power dissipation against comparison with conventional divider using repeated subtraction. The designs were implemented using industry standard Cadence® software using 45nm technology library. The design has been validated on FPGA Spartan-3E kit. The validation results show appreciable reduction in circuit latency and in Look-Up-Table (LUT) utilization using proposed Vedic divider than the conventional divider. © 2014 IEEE.