This paper proposes and implements an energy efficient, high speed pipelined Multiply and Accumulate (MAC) architecture for DSP applications. A controller has been designed to detect the input pattern such that it bypasses multiplier and accumulator units depending on the consecutive input bits. This architecture is used for both signed and unsigned multiplication, it includes a guard bits to support longer iterations and a saturation circuitry to provide a maximum range in the output. This technique of bypassing the paths/modules in the architecture makes its more energy efficient and reduces its critical path when applied on combined MAC architecture which has proved to be high speed compared to other conventional MAC architecture and a power reduction of 28% is achieved. The proposed MAC architectures are modeled using Verilog HDL and implemented for different operand sizes i. e. 8, 16, 32. The design has been synthesized using RTL compiler from Cadence with TSMC 90nm Technology, place and route is carried out using Cadence Encounter. © 2012 ACM.