The clock distribution circuit dissipates a significant portion of total power in today's processors. Thus, there is a great opportunity for reduction of power in the clock distribution circuit. The energy recovery technique proves to be a most appropriate approach in such a condition. This paper uses energy recovery technique for the recovery of power from the clock tree distribution network. The work results in reduced delay overhead by less than 7% and it achieves a power reduction of 93% against the conventional clocking. Increased levels of clock distribution from 2 to 16 levels have been employed. The use of buffers has been eliminated, and this results in lower area. Proposed design operates at higher range of frequencies, i.e., up to 400MHz and also at different switching rates of 20%, 30%, 50% and 100%. Conditional capturing technique is utilized for low data switching activity. The clocking system has been laid out through full-custom approach, and it is made of hierarchical type. The design is being implemented using the industry standard EDA tool and 180nm technology library. © 2014 IEEE.