The computation of FFT has become necessary in almost all DSP based applications and image processing applications. The radix-22 feed forward (MDC) FFT architecture originated for the systems which require high performance. The architecture uses both trivial and non trivial rotators for the computation of FFT. This paper proposes a switch logic in place of trivial rotators thereby reducing computational complexity. The compilation, elaboration and simulation of the design is done using NC launch tool. The design has been synthesized with 130 nm, 90nm, 45nm CMOS technologies using Cadence RTL compiler. The timing, power and area savings are of 26.2, 66, 23.4 percentage respectively for the proposed design. Therefore this design could be used for the systems which demand reduced area, low power and high performance. © 2005 - 2014 JATIT & LLS. All rights reserved.