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Low power floating point computation sharing multiplier for signal processing applications

Sivanantham S., , Balamurugan S., Bhuvana Phaneendra D.
Published in
Volume: 5
Issue: 2
Pages: 979 - 985
Design of low power, higher performance digital signal processing elements are the major requirements in ultra deep sub-micron technology. This paper presents an IEEE-754 standard compatible single precision Floating-point Computation SHaring Multiplier (FCSHM) scheme suitable for low-power and high-speed signal processing applications. The floating-point multiplier used at the filter taps effectively uses the computation re-use concept. Experimental results on a 10-tap programmable FIR filter show that the proposed multiplier scheme can provide a power reduction of 39.7% and significant improvements in the performance compared to conventional floating-point carry save array multiplier implementations.
About the journal
JournalInternational Journal of Engineering and Technology
Open AccessNo