High-performance and low-power are the two main criteria in modern digital design. Based on the idea of sharing two adders used in the Carry Select Adder (CSA), a new design of a low-power high performance adder is presented. The new adder is faster than a Ripple Carry Adder (RCA), but slower than a CSA. On the other hand, its area and power dissipation are smaller than those of a CSA. © Research India Publications.

Sakthivel R

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Kittur Harish Mallikarjun

Kerur S.S

Girish V.A.

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

2017 International conference of Electronics, Communication and Aerospace Technology (ICECA)

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-μm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA. © 2010 IEEE.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Low-Power and Area-Efficient Carry Select Adder

Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC

Journal	Data powered by Typeset2017 International conference of Electronics, Communication and Aerospace Technology (ICECA)
Publisher	Data powered by TypesetIEEE
ISSN	09734562
Open Access	No