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Low power, low phase noise based phase locked loop and its design implementations
Published in Blue Eyes Intelligence Engineering and Sciences Publication
Volume: 8
Issue: 6
Pages: 1139 - 1143
In this work, we have discussed a new approach in designing the phase-locked loop (PLL), the proposed circuit is designed with the GDI cell-based PFD, charge pump and low pass filter. For frequency matching and for larger locking state, the design used as D flipflop from the TSMC library. It is used as frequency synthesizers and divides the incoming frequency by 2.This design uses 5 stage current starved voltage control oscillator (CS-VCO). The designed PFD is free from the dead zone issue and it is suitable for the low power applications. the designed PLL works for an average frequency range of 8 GHz and its offset frequency is targeted at 1GHz.This PLL model has low phase noise of -112 dBc/Hz at 1 Mhz frequency which is quite standard and the power consumption of the circuit is 8 μW. The entire work is simulated using Cadence Virtuoso 45 nm Technology. © BEIESP.
About the journal
JournalInternational Journal of Innovative Technology and Exploring Engineering
PublisherBlue Eyes Intelligence Engineering and Sciences Publication