This paper presents a low power modulo 2n+1 multiplier in which one input and output uses the weighted representation while the other input uses the diminished-1 representation. The low power in the multiplier is achieved by reducing the number of transition or transition frequency in the adder tree which is used to reduce the partial product and data aware properties is achieved with the help of the master and slave latches, dynamic range detection unit and the bit restoration unit. The dynamic range detection unit detects the dynamic range between the input data's and it allows only those data for the further processing in the adder unit and bit restoration unit take care of the data bit which is lost during the addition. The multiplier proposed in this paper form only n/2 (n=number of input bits)partialproduct which is less than all the partial products produced by the available multiplier. Although by applying this logic there is a area overhead but there is a increase in power saving from 32% to 77% as the number of bits in the input of the multiplier increases from 4 to 32 bit. © 2015 The Authors.