Due to continuous scaling down of VLSI based design technology, it has become extremely important to consider the role of Clock Tree Synthesis (CTS) in deciding the performance of complex nanometer chips. Skew minimization with less power dissipation improves efficiency of CTS. This Paper presents Skew aware clock tree routing with obstacles present in the routing path. Thus blockage modeling is incorporated with sorting based partition of points to reduce wire snaking. The routing is based on an efficient algorithm which generates the clock tree, performs merging of points and finally determines the tapping point. Experimental calculations demonstrates the efficiency of our CTS approach with effectively improved skew and Latency by 46% and 57.8%. Moreover our Merge sorting obtains a significant reduction in Power by 75.9% compared to bipartition algorithm. The look up table is built using NGSpice tool to achieve the desired results. © 2017 Taylor & Francis Group, London.