In this paper, A Low Power Pre-charge Free Dynamic Content Addressable Memory is Proposed, it is one of the most significantly used Hardware search Engine in Modern Computing, Security Systems and in areas needing fast Memory Access. It is not only a Data Storage Device but also designed to search its own memory in single Cycle. The CAM is introduced in low power Parallel look up search Applications. A Proposed Low Power 6-T DCAM cell consuming power less than 93% and 43% than PF-DCAM and PF-CAM cells is introduced in Hardware Search Engine. 8∗8 CAM Architecture of the proposed scheme is implemented using Cadence GPDK 45nm Technology. © 2019 IEEE.

Ragunath G

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Subba Rao Naidu Immadisetti C.V

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

2019 International Conference on Vision Towards Emerging Trends in Communication and Networking (ViTECoN)

Content-addressable memory (CAM) is a hardware device which stores lookup data in the memory and searches that data parallel within a single clock cycle. Conventional CAM operates in three phases which are writing the binary data in the memory, pre-charging, and evaluating the match line (ML). Recently, it is identified that CAM with precharge ML consumes more power due to the short circuit current path. To overcome this problem, here, we proposed CAM architecture without applying precharge to ML which helps to operate CAM with low power and high performance. The precharge-free CAM works on two stages writing and evaluation. This paper compares conventional precharge-based ML architecture like NOR CAM and master-slave CAM of 1 (word) × 8 (bits) with a proposed design for power consumption at different mismatches. Simulations results show that when compared to conventional designs, the proposed design minimizes approximately from 86 to 88% of average power. © Springer Nature Singapore Pte Ltd. 2019.

Lecture Notes in Electrical Engineering Microelectronics, Electromagnetics and Telecommunications

Efficient Precharge-Free CAM Match-Line Architecture Design for Low Power

Content-addressable memory (CAM) is the hardware for parallel lookup/search. The parallel search scheme promises a high-speed search operation but at the cost of high power consumption. Parallel NOR- and NAND-type matchline (ML) CAMs are suitable for high-search-speed and low-power-consumption applications, respectively. The NOR-type ML CAM requires high power, and therefore, the reduction of its power consumption is the subject of many reported designs. Here, we report and explore the short-circuit (SC) current during the precharge phase of the NOR-type ML. Also proposed here is a novel precharge-free CAM. The proposed CAM is free of the drawbacks of the charge sharing in the NAND and the SC current in the NOR-type CAM. Postlayout simulations performed with a 45-nm technology node revealed a significant reduction in the energy metric: 93% and 77% lesser than NOR- and NAND-type CAMs, respectively. The Monte Carlo simulation for 500 runs was performed to ensure the robustness of the proposed precharge-free CAM. © 2016 IEEE.

Journal	Data powered by Typeset2019 International Conference on Vision Towards Emerging Trends in Communication and Networking (ViTECoN)
Publisher	Data powered by TypesetIEEE
Open Access	No