With advent of technology scaling, the prime objective of design i.e. low power consumption can be easily acquired. For any digital logic design the power consumption depends on; Supply voltage, number of transistors incorporated in circuit and scaling ratios of the same. As CMOS technology supports inversion logic designs; NAND & NOR structures are useful for converting any logic equation into physical level design that comprises of PMOS and NMOS transistors. In similar way, logic can be implemented in other styles as well, with the difference in number of transistors required. The conventional CMOS design for XOR logic can be possible with 8 or more than 8 transistors, with the methodology discussed in this paper, the same design for XOR logic can be made possible with 6 transistors. The proposed methodology consists of Pass transistor logic and Single feedback topology. This design consumes 50% less power than that of conventional XOR logic design with CMOS technology. Since the design for XOR logic, is useful for variety of applications such as Data encryption, Arithmetic circuits, Binary to Gray encoding etc. the XOR logic has been selected for design. The design explained in this paper is simulated with Cadence 90nm technology. © 2017 IEEE.
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|Journal||Data powered by Typeset2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN)|
|Publisher||Data powered by TypesetIEEE|