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Memristor-based 2D1M architecture: Solution to sneak paths in multilevel memory
Published in Wiley Blackwell
Volume: 32
Issue: 1
The memristor, the fourth fundamental elements have shown the potential to revolutionize the present storage, analog, and digital computational technologies. The ability to remember its previous state in the absence of any stimuli has made the memristor as a prime candidate for nonvolatile memory. However, the sneak path is one of the main problems hampering the implementation of memristor-based crossbar memories. In this article, we introduce a new crossbar architecture that is capable of storing multibit per cell and eliminates the sneak paths without adding any complex circuitry. The approximate write delay of the proposed memory cell is 20 mS which is very close to the delay of the single bit cell. The proposed architecture was validated by storing four different logic states in each cell of the 4 × 4 memory. Hence, one memory cell of the proposed architecture replaces four cells of the single-bit memory at the cost of one additional diode per cell. Therefore, the proposed scheme saves considerable area when compared with the conventional single-bit memory array. The write/read operations are validated by a generic, accurate, and efficient “voltage threshold adaptive memristor” (VTEAM) model. The simulation results prove that the proposed circuitry can read the memory content even after 2000 cycles without any sneak paths problem. © 2020 John Wiley & Sons Ltd
About the journal
JournalData powered by TypesetTransactions on Emerging Telecommunications Technologies
PublisherData powered by TypesetWiley Blackwell