Memristor memory has got outstanding characteristics to replace the present memory technologies. The advantages of memristor memories include non-volatility, high density, low power consumption, fast operating speed, and ability to function as multi-level cell. In spite of having numerous advantages, they are highly prone to process variations. Fault analysis shows that there are exclusive faults occur in memristor in addition to other traditional memory faults. Several latest research works are trying to address these issues by different schemes. This paper aims to summarize the recent research progress in terms of memristor faults, fault modeling, testing, and testability schemes. © 2017 Pushpa Publishing House, Allahabad, India.

Ravi V

Electronics

School of Electronics Engineering

Chennai Campus

Prabaharan S.R.S.

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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Memristor based memories: defects, testing, and testability techniques

Far East Journal of Electronics and Communications

The non-deterministic nature of memristor and its unreliable behavior are the two major concerns hampering its growth and industrial manufacturability. The endurance and reliability of memristor memories are affected not only by the process variations (intrinsic), but also due to the electrical stress created by interfacing peripheral circuits (extrinsic). Concerning the intrinsic faults in transition metal oxide (TMO) memristors, drifting of oxygen vacancies across the device is responsible for SET/RESET operation. It is likely that such drifting might induce switching faults during the device operation, for instance endurance of the memory. Thus, the application of a fixed write pulse may not suffice to achieve successful write operations under these circumstances. To circumvent the above pitfall, we propose here a new technique by designing a fault tolerant adaptable write scheme which can adapt by itself based on the behavior and switching faults. Accordingly, the proposed write scheme identifies the optimal amplitude and the width for write pulse. The proposed write scheme under various memristor faults is found to enhancing the reliability of memristors efficiently. Further, the results are validated by means of Monte-Carlo analysis by infusing the random variations of internal parameters of memristors as well. © 2018 Elsevier GmbH

Journal	Far East Journal of Electronics and Communications
Publisher	Pushpa Publishing House
ISSN	0973-7006
Open Access	0