In today’s digital era, the device size, speed and power consumption are regarded as the most sought-after design constraints of battery powered embedded gadgets. The emerging computing paradigm called “approximate computing” can be applied to fulfil the said constraints by compromising the accuracy through inexact hardware design techniques. Inherent error resilient applications viz., image, media processing etc., are well suited for approximate computing. Nevertheless, certain niche applications may demand better accuracy levels than the fully approximated output. Since adders are the basic building blocks of all arithmetic operations involving the said applications, the specific architecture involving these blocks greatly influence the efficacy of the system design. Accordingly, a new architecture is proposed in which a fusion of accurate-approximate 8-bit adder and subtractor design is developed employing memristors as both logic elements and memory components. Besides the system level validation involving the designed architecture, the standard performance metrics are deduced by employing MATLABtools and the new accurate-approximate 8-bit architecture thus designed yields better accuracy as expected. © BEIESP.